Uvm testbench not proceeding beyond time 0

UVM
1

EDA link

I have this UVM test bench, but it seems not to proceed beyond time 0. I have checked these things, but i am not exactly sure what’s going on here. can somebody take a look and see whats going on here? Appreciate the help.

  1. Raise and drop objections in the test.
  2. Connection between sequencer and driver.
2

You are raising objection at time 20 units and not at time 0.
As a result your simulation ends at time 0 itself.
Within class ‘vend_test’ change the run_phase to ::

task run_phase(uvm_phase phase);
    vend_seq seq;
    phase.raise_objection(this); // Added this line so that objection is raised at time 0
    seq = vend_seq::type_id::create("seq");
    `uvm_info("vend_base_test","running from test",UVM_NONE)
    //wait(vif.rst);
    #20;
    //phase.raise_objection(this); // can be removed 
    seq.start(env.agt.sqr);
    phase.drop_objection(this); 
  endtask
3

Thanks !