UVM test finishes immediately

In reply to mreister:

Your environment is acting exactly as it should:

  • Your test raises an objection and starts one sequence
  • Your sequence body creates one sequence_item and calls start_item()/finish_item() to send it to the agent sequencer
  • The agent driver gets the one sequence_item from the sequencer
  • The driver calls do_drive(), which has only one timing construct: @(posedge virtual_interface.clk);
  • Once this timing construct detects the posedge of the clock, it will complete the data/valid assignments
  • The sequence_item is now finished
  • The sequence is now finished
  • The test drops the objection and the simulation exits

This is why you see the test finish immediately on the first posedge of the clock. If you add a drain_time(), you can run longer.