UVM Register Model with mixed width registers

In reply to dbrown123:

I have the same issue using 3rd party IP,
For 64 bit submaps the create_map is set to 8 bytes however the top reg map sets the n_bytes to 4,
On a 64 bit wide bus we shouldn’t expect two transactions for a 64 bit wide register right ?
Can you share what you fixed in the reg adapter to fix the problem ?