UVM register model: strange uvm_error message

In reply to Vinay Jain:

Hi Vinay Jain,
I appreciate it if we investigate the message again.
It says:

writing 0 in bit #0 of a register with initial value 'h01 yielded 'h00

which means in the RTL, the register is RW.
I’ve checked the register classes and made sure the field is defined as “RW”. Actually the whole register’s fields are defined as “RW”. So why the sequence expects the result to be 'h01 instead of the correct one 'h00 !

Thanks