In reply to Mustafa:
The problem is for all “RW” fields
Another example:
UVM_ERROR verilog_src/uvm-1.1d/src/reg/sequences/uvm_reg_bit_bash_seq.svh(175) @ 143600000000: rgm_seq.reg_single_bit_bash_seq [uvm_reg_bit_bash_seq] Writing a 1 in bit #1 of register “spi_rm.reg_0x27” with initial value 'h0000000000000020 yielded 'h0000000000000022 instead of 'h0000000000000020
What is stated is correct, so why does it consider it as an error?