Verification Academy
UVM register model: strange uvm_error message
UVM
error
,
UVM-Register-Built-in-sequence
,
UVM-system-verilog
,
uvm-register-sequences
,
UVM
Tudor_Timi
April 1, 2015, 12:05pm
2
In reply to
Mustafa
:
Are you sure the field isn’t declared as read-only?
show post in topic