Uvm register model coverage when register type is Write one to clear

Coverage
1

Hi,
In my register model there are some interrupt registers of type “write 1 to clear” .
Even though i am writing “1” after reading(interrupt raised) from test bench to clear the registers, coverage shows only 0 is covered for write.

please help me to resolve the issue.

2

This should be the expected behaviour right ?

There would not be any exclusive write for a value of 1, instead this might be written from the RTL itself I guess, when it sees a interrupt or so.

Not sure if UVM reg coverage would look at the attribute of the register…