Just to report on this bug and close off this ticket.
I have spent at least a week and a half trying to track this down, and with the help of a Mentor FAE we have came to the conclusion that there is a proper clanger in the way Register Generator creates verilog registers from VHDL registers.
The main focus is what you specify in the “Field Backdoor” column of the source spread sheet.
In the regs worksheet if we specify the Field Backdoor = FIELDA_status_reg_h.
In the Verilog RTL the register name matches the Field Backdoor path specified in the spreadsheet. e.g.
always @ (posedge clk or posedge rst)
begin : reg_status_reg_fielda_status_reg_h
//Reset
if (rst)
FIELDA_status_reg_h <= 1'b0;
//SW: read-write
else if (wen_status_reg_h)
FIELDA_status_reg_h <= wdata[0];
end
There is subtle difference in the VHDL RTL that is generated from the same register map.
The register name is : FIELDA_status_reg_h_buf. The signal FIELDA_status_reg_h is connected to the register output.
reg_status_reg_fielda_status_reg_h : PROCESS (clk, rst)
BEGIN
--Reset
IF (rst ='1') THEN
FIELDA_status_reg_h_buf <= '0';
ELSIF (clk'EVENT) AND (clk ='1') THEN
--SW: read-write
IF (wen_status_reg_h = '1') THEN
FIELDA_status_reg_h_buf <=wdata[0];
END IF;
END IF;
END PROCESS reg_status_reg_fielda_status_reg_h;
--Asign internal buffer value to output
FIELDA_status_reg_h <= FIELDA_status_reg_h_buf;
The result of this is that if you are creating registers with Register Generator you need to ensure that the field column of the source spread sheet has “_buf” appended to the name specified in the “Field Backdoor” column.
I am massively disappointed in the Mentor for this. With the Register Assistant now in version 4.5 these sort of details should be crystal clear in the documentation. It feels like the register generator has not been tested correctly for VHDL duts.
The comment in this other post still applies about leaving a delay between frontdoor writes and backdoor reads.