Uvm reg block override using factory override

UVM
1

Hi All,

i have 3 different actual reg blocks which are extended from uvm_reg_block. i want to use a single reg block at a time in my simulation , how to use factory override on 3 reg blocks which are directly extended from uvm_reg_block

example blocks like below:
class A extends uvm_reg_block;
class B extends uvm_reg_block;
class C extends uvm_reg_block;

i want to use one reg block in my env and reuse all my sequences without using any compile ifdefs.

kindly provide me suggestions.

Thanks,
Bala

2

I am not clear on the need to use factory override in this case.
You should instead define a top_reg_block which has all these 3 reg_blocks as sub-blocks.
This top_reg_block would act as your root register block.

Based on this idea for Sub-system level Tb’s we re-use each of the IP’s reg_block as sub-block of our user-defined ss_top_reg_block

3

we did this top reg block wrapper with sub blocks at subsytem level tb. but my question is how to use only one block at a time instead of creating 3 blocks and building 3 models. IP level, we need to use only 1 block from 3 available reg blocks without using compile defines ifdef.

4

Within build() function of top reg block you would instantiate these 3 sub-blocks and call configure , build , add_submap for them.
Then in your env ( or any tb component ) you simply need to instantiate the top_reg_block and call it’s build function

Each IP could access the respective register block via top_reg_block_h.ip1_reg_block / top_reg_block_h.ip2_reg_block / top_reg_block_h.ip3_reg_block

5

What is the actual difference between the uvm_reg_block: A, B and C?
Number of registers?
Different registers’ addresses?
Different functionality of the registers?

It could help in clarifying the need in factory override…

6

In general, you can’t override a class using the factory unless the base class is registered with the factory, which uvm_reg_block is not. To overcome this limitation, you need to create a common block base class that encapsulates all the members you want to access. This is why it’s crucial to understand the differences between these various blocks.

7

Hi Dave and Michael,
The difference between these blocks: A block is super set and B/C blocks are sub set of super block A. But when RAL blocks are generated using systemRDL, all 3 blocks are extended from uvm_reg_block independently.
So, i would like to access only 1 block instead of creating and building 3 blocks all the time for my simulations and avoid using ifdef.