In UVM 1.2 library uvm_put_port extends uvm_port_base but uvm_port_base does not contains any declaration or definition of function or task such as try_port,put_port. Then how its been inherited?
In reply to jayeshranjan:
Hi,
In below snippet type IF is uvm_tlm_if_base#(). That’s the abstract class from where all task/function like put(), try_put, transport(), write() etc comes.
virtual class uvm_port_base #(type IF=uvm_void) extends IF;
// CLASS: uvm_*_port#(T)
class uvm_put_port #(type T=int)
extends uvm_port_base #(uvm_tlm_if_base #(T,T));