UVM phases corresponding to SV Regions

Hello Dave,

I’m currently struggling with a testbench with several agents that I need to run in Strato. My main concern is that the testbench is written as a program and changing in to module generates a load of errors (I suspect these errors come from the UVM queues and checkers being misaligned because of how events are executed from Program vs Module.
Is there a strategy you may recommend to follow to fix the testbench to match the “program” behavior? I don’t care if we have to use non-synthesizable code now (that I can fix later).

Appreciate any suggestions you may have.

– Hector.