UVM phases corresponding to SV Regions

UVM
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4

Hi Dave,

You mentioned :

However, all UVM phases execute in the active SystemVerilog event region.

But this should happen if the top of the UVM Testbench is declared as “module” correct?
If the UVM Testbench top is declared as “program” then the execution of UVM phases will happen at the REACTIVE region of SystemVerilog, right?

Can you please confirm?

Thank you.