In reply to mukul1996:
In some respects you can say that the UVM phases are similar to the simulation stages of elaboration, run-time execution, and termination. However, all UVM phases execute in the active SystemVerilog event region.
Some of the UVM phase names come straight from SystemC, like
end_of_elaboration and
start_of_simulation also mimicking the stages of simulation. The major difference between the elaboration stages of simulation, and the similar stages in UVM and SystemC is they are all executing at run time. We can randomize and dynamically modify the testbench architecture. That is something that cannot be done with the elaboration of an RTL DUT.