In reply to chr_sue:
Points 1 and 2 Agreed and I will change that. Mentor has a framework generator which is what I used, but it was setup for HW emulation and I didn’t want to use that but I wanted to take some of the generated files for my approach. So I need to fix that.
What I am really trying to do is create a testbench that can be scaled easily without having to use a generator. Just code the pieces you will need to code anyways even if you have a generator.
The test tells how many agents (and eventually what scoreboards the outputs will be connected to). So the person modifying the testbench only needs to code the driver, monitor, transaction,coverage and scoreboards. From the test top they specify what pieces will compose the agent/s.
Some people think of the agent as defined by the transaction data and some people think of the agent as the as defined by the interface it drives. I can see it from both sides and would like the ability to mix and match at will.
Maybe this will end up being impractical but I have done something similar in systemverilog and I found it very quick and easy to modify for my needs (FPGA verification).
Thanks for the reply,
Scott