In reply to abs:
I believe I understand where the problem is. Actually my simplified example doesn’t represent all the details for simplicity, but is hiding an important aspect of the whole story. The base_object in my case is actually parametrized with a type and the specialized version of it specifies the type. Therefore it is more like:
class base_object #(type T = int) extends uvm_object;
// utils and other stuff omitted
T a;
endclass
class extended_object extends base_object #(real);
int b;
endclass
The end result is that those two classes, even though extending one another, are not type compatible, resulting in SystemVerilog to prevent assigning one handle to the other one.
At this point, how could I achieve what I want, maintaining the ability to have the base_object parametrized? Or should I simply give up on that idea?