Hi,
There are inconsistencies that should be resolved in your test bench.
- In testbench.sv
You forgot to set the reset to 1 after you change it to 0, so your memory is always resenting all registers.
…
initial begin
rst = 1;
10 rst = 0;
10 rst = 1; //======= Add in your code
end
…
- In driver:
In your reading task you use non-blocking assignments,
vif.driver_cb.wr <= req.wr;
vif.driver_cb.addr <= req.addr;
req.rdata <= vif.driver_cb.rdata;
So your rdata is the current interface rdata and not the read from the requested address, since all three assignments occur in parallel. But switching them to blocking assignments is not enough, since your DUT needs a clock pulse to answer a read request. So to resolve this you should wait a clock pulse before copying rdata.
…
@ (vif.driver_cb)
req.rdata = vif.driver_cb.rdata;
…
This solves your reading problem, I hope I helped.