I'm trying to run a sequence (seq_write) for certain number of times from another sequence (seq_wr_rand) using `uvm_do. The base sequence has a variable updated through get config_db.
The problem is, seq_wr_rand is getting the proper config_db value, whereas the sequence being called (seq_write) from it is not getting the config_db value and my test fails. I'm expecting write with value x61, whereas the actual is x14. The code & output snippets are below.
Similar to this, i've many like this. Can someone plz tell what things i'm doing wrong to get output like this???
CODE:
class base_sequence extends uvm_sequence #(data_item);
bit [9:0] addr_cfgd=20;
dev_config cfg;
`uvm_object_utils(base_sequence)
function new(string name="base_sequence");
super.new(name);
endfunction
virtual task pre_body();
super.pre_body();
if (starting_phase!=null) begin
starting_phase.raise_objection(this);
end
if(!uvm_config_db #(dev_config)::get(null, get_full_name(), "dev_config", cfg))
`uvm_fatal(get_type_name(), "dev_config config_db lookup failed")
addr_cfgd=cfg.addr_cfgdve_address;
`uvm_info(get_type_name(), $sformatf("addr_cfgd = x%0h",addr_cfgd), UVM_FULL )
endtask
endclass : base_sequence
class seq_write extends base_sequence;
`uvm_object_utils(seq_write)
function new(string name = "seq_write");
super.new(name);
endfunction
task body();
data_item req;
begin
`uvm_info(get_type_name(), $sformatf("Executing WRITE @ x%h",addr_cfgd), UVM_LOW)
req = data_item::type_id::create("req");
start_item(req);
assert(req.randomize() with {reqst == WRITE;address == addr_cfgd;});
`uvm_info(get_type_name(),$sformatf("%s reqst %s: addr = `x%0h, data.size = `x%0h",get_sequence_path(), req.reqst,req.address, req.data.size()),UVM_FULL);
finish_item(req);
end
endtask
endclass:seq_write
class seq_wr_rand extends base_sequence;
rand shortint [5:0] count;
`uvm_object_utils(seq_wr_rand)
constraint limit {count > 0; count < 10;}
function new(string name = "seq_wr_rand");
super.new(name);
endfunction
virtual task body();
seq_write req_wr;
begin
`uvm_info(get_type_name(), $sformatf("Executing WRITE for %0d times...", count), UVM_LOW)
repeat (count) begin
`uvm_do(req_wr)
end
end
endtask
endclass:seq_wr_rand
Simulation Output:
UVM_INFO seq_lib.sv(48) @ 0.0ns: uvm_test_top.env.my_agnt.sequencer@@seq_wr_rand [seq_wr_rand] addr_cfgd = x61
UVM_INFO seq_lib.sv(211) @ 0.0ns: uvm_test_top.env.my_agnt.sequencer@@seq_wr_rand [seq_wr_rand] Executing WRITE for 3 times…
UVM_INFO seq_lib.sv(180) @ 0.0ns: uvm_test_top.env.my_agnt.sequencer@@seq_wr_rand.req_wr [seq_write] Executing WRITE @ x014