In reply to vishwesh:
The UVM library exists as a standard for writing testbenches in SystemVerilog. A proof-of-concept UVM-SystemC library was released for review over a year ago, and there has been no further activity since that release. I suspect to use it, you will have to already know SystemC and some SystemVerilog UVM as there is no other information on it other than what is on the Accellera FAQ page.