Hi,
I have a memory array with ~50,000 entries, each entry takes about 1KB.
I want to preload all of the array with random data.
To do this, I use uvm_hdl_deposit to write backdoor to the RTL array HDL path.
The use of uvm_hdl_deposit uses the highest amount of memory in the test compared to the other test parts.
A test that took ~5GB of memory - ~2GB of memory is used on uvm_hdl_deposit DPI calls.
I was wondering if there is a better performing method of writing to an HDL path.
It depends on how your memories are modeled. Are they high-level RTL as Verilog arrays, or gate-level/user-defined primitives? i.e. are you depositing one memory element at a time?
Some tools have special commands to randomly initialize memories.
My memories are modeled using Verilog arrays but low level.
I create an array of classes as part of a uvm component run in data phase.
Each class describes a logical array entry.
But, the actual RTL array is not sorted logically - Each logical array entry needs to write to a HDL path hierarchy according to a hash function on the address.
For each logical entry I need to write to several HDL paths to preload.
For example - if am preloading address X to the RTL array, the HDL paths I will need the write data to are:
<path_to_mem_array>.module_a[hashA(X)].module_b[hashB(X)].array
<path_to_mem_array>.module_a[hashC(X)].module_b[hashD(X)].array
<path_to_mem_array>.module_a[hashE(X)].module_b[hashF(X)].array
For each I will write a different chunk of data.
Currently I am doing it using uvm_hdl_deposit.