Hi,
I would like to use only System Verilog not UVM in my testbench. But I would like to make my system Verilog testbench to behave like UVM. How do I do it? Like UVM is using phases, Factory, TLM etc. How to create similar behavior just by using only System Verilog in the testbench?
UVM is SystemVerilog.
If you want all of the features of the UVM, but not call it UVM, you can copy its source in SystemVerilog and remove the UVM prefix from all the identifiers. What is the point in doing that?
Hi Dave,
Thanks for replying. I have a SystemVerilog testbench which doesn’t use UVM concepts like TLM, phases and factories. But since in UVM these are much strong features, I would like to get similar behavior without using UVM. This is what I wanted to achieve. Doing so, I believe this testbench can be easily plugged into a UVM testbench, and I think will be highly reusable the way a UVM testbench does.
It seems like you’re trying to get the features of UVM without using the actual UVM source code. To do that, you’d need to make a copy of the UVM source code and then remove the three letters U, V, and M from the copy. Once you’ve done that, the copy won’t be UVM anymore. What is your point of not using the original UVM source code?