UVM_FATAL: default timeout of 9200 hit, indicating a probable testbench issue

In reply to jpms.suresh:

This means 9200s simulation time passed and stop_request() was not called. This is a large number, does your test/sequences need all of that time (and more) to finish?
→ If yes, you can change that default number via set_timeout() method.
→ If no, then perhaps check for objections that were raised, but never dropped.