I have a DVCon paper for that!: Using Parameterized Classes and Factories: The Yin and Yang of Object-Oriented Verification explains the mechanisms behind the UVM’s factory.
When we use the term register with the factory, we are adding an entry into a static table taking advantage of the behavior of parameterized classes in SystemVerilog. The macros uvm_compoenent_utils /uvm_object_utils create specializations of the parametrized classes that have the static methods like create that work with the factory. I have another article that explains how the macros work.
The factory and the config_db do have similar use models for specifying overrides, but they are completely separate from each other. The config_db is just a generic database for storing values of any type. The factory stores proxy class objects as described in the DVCon paper in its database and then constructs the desired class.