UVM End of test

UVM
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15

In reply to chr_sue:
Thanks for the response and your time. Below this text is a pseudo-code to explain the problem statement.

Few points -

  1. Currently enb is equal to 2’b11, so we are running both the threads in parallel and queueRec2 and queueRec1 are the two queues.
  2. Whenever the monitor writes into the analysis port, transactions reach to scoreboard through the analysis port to these queues.
  3. When the queue’s size becomes non-zero, data is popped from the back of the queue.
  4. In the code you can also see those relative write methods for the respective analysis port. Through these display messages, in one such simulation, I come to know that the monitor has written into the Port 10-times.
  5. But the debugger print message in thread1 and thread2 I find the prints only 6 times. At the same time, the queue’s Write Print is showing it got entries inside it.
task scoreboard::write_rec2(input seq_item tr);
 seq_item pkt = new();
 pkt.copy(tr);
 queueRec2.push_front(pkt);
 $display("Queue Got this data: %0h",pkt.data);

endtask
task scoreboard::write_rec1(input seq_item tr);
 seq_item pkt = new();
 pkt.copy(tr);
 queueRec1.push_front(pkt);
 $display("Queue Got this data: %0h",pkt.data);
endtask

task scoreboard::run_phase (uvm_phase phase);
  forever begin
     if (enb == 2'b11) begin
	fork 
		begin thread1(); end
		begin thread2(); end
	join
     end
     else if (enb == 2'b10) begin
	thread1();
     end
     else if (enb == 2'b01) begin
	thread2();
     end
  end
endtask

task scoreboard::thread2();
	wait (queueRec2.size != 0);
	Rec2 = queueRec2.popback();
	$display("Queue Received this Data: %0h", Rec2.data);
	wait (queueTrans2.size != 0);
	trans2 = queueTrans2.popback();
	compare(trans2.data,Rec2.data);  // this function two inputs and check equality
endtask

task scoreboard::thread1();
	wait (queueRec1.size != 0);
	Rec1 = queueRec1.popback();
	$display("Queue Received this Data: %0h", Rec1.data);
	wait (queueTrans1.size != 0);
	trans1 = queueTrans1.popback();
	compare(trans1.data,Rec1.data);  // this function two inputs and check equality
endtask

task monitor:: run_phase(uvm_phase phase);
	forever begin
	  sample_data();
	end 
endtask 

task monitor:: sample_data();
	for (int i = 0; i < 16; i++) begin
		@(posedge clk iff(rdy && vld));
		out_tr.data[i] = vif.databit;	// out_tr.data is an array of 16, storing databit (which is of single bit) at every rdy && vld.
	end 
	anlysis_port.write(out_tr)
endtask

I will look into your suggestion of using fifos instead of queues. but I am not able to understand what leads to this behaviour. I have read somewhere in the blog due to some delay in 
the testbench environment's components sometimes the scoreboard can't process kinds of stuff and ends up being broken. Except for these very high-level thoughts, I haven't seen much info about the theory. Can you please share some thoughts about this side too if you think that's a possibility....?