In reply to mayurkubavat:
It’s clear regarding READ-recoding in monitor.
Thanks a ton for your clarification, Mayur.
Regardsing driving ‘Z’ in driver, while reading,
//Pseudo code:
//Inside Interface.sv
wire SDA;
..
clocking driver_cb @ (posedge clk);
default input #1ns output #1ns;
inout SDA; // since its bi-directional
endclocking: driver_cb
// Inside Driver.sv
vif.driver_cb.SDA = req.sda; // is made as 'Z', with the help of 'req.sda' variable in sequence
Is this implimentation right ?
I’m sorry if I’m getting in detail, this will be my last query regarding this!
I really wanted some clarification on these 2 things to proceed further!
Thanks again!!