In reply to Vaino:
The uvm_component class builds the hierarchy and will provide a cryptic unique name for your object if you don’t provide a name. So it’s better to provide a name that makes sense to you for reporting and debugging. Debugging with a UVM-aware tool becomes a lot easier if the component name matches the class variable name that holds the component handle.
The reason the UVM has to manage the hierarchy is that the SystemVerilog Object-Oriented Programming model does not have a static class instance concept, like module instances in Verilog. There is no such thing as a parent/child class unless you have a methodology to add class properties to your object that represent that relationship. A class variable can only hold a reference to another class object - it is up to the methodology to distinguish whether that object “belongs” to it or not.