UVM backdoor register access without register names in RTL but only fields are present

UVM
1

Hi there,
I am setting up the backdoor access for our project. I found out that in the register RTL, we don’t have register names. Instead only field names are present. Is there a way that I can use UVMBACKDOOR access for fields without the register names present in the RTL?
I referred to the UVM user-guide 1.2, section 5.6.2 and tried with add_hdl_path_slice like as below (example from 5.6.2)

  if(lookup_flds.exists(fname)) begin
            uvm_reg parent_reg = lookup_flds[fname].get_parent();
            parent_reg.add_hdl_path_slice(hdl_path, lsb, size, is_first, kind);
         end

(Field names are present in a file which is read in the above code)

 **I tried to write using write() and poke() methods** 

rdata[12] =1;
`IMPL_SPECIFIC_REG.mb_txctrl_reg0.load_speed_cnt_over_en_preg.write(status,rdata, UVM_BACKDOOR);
 `IMPL_SPECIFIC_REG.mb_txctrl_reg0.load_speed_cnt_over_en_preg.poke(status,rdata);

I get this warning

“No backdoor access available for field ‘regmodel.cdn_ucie_impl_specific_reg_map_impl_specific_ctrl_cdbreg.mb_txctrl_reg0.load_speed_cnt_over_en_preg’ . Using frontdoor instead.”

When I tried without register name:

`IMPL_SPECIFIC_REG.load_speed_cnt_over_en_preg.write(status,rdata, UVM_BACKDOOR);

 `IMPL_SPECIFIC_REG.load_speed_cnt_over_en_preg.poke(status,rdata);

I get the compilation error as

“load_speed_cnt_over_en_preg” is not a class item.

The register names are present in register XLS file but the RTL regmap contains only fields. The regmodel is generated with registers class (uvm_reg) and fields inside the class.
Can anyone tell me is there a way I can access fields through backdoor without registers in the RTL?