UVM Agent connect phase error connecting driver to sequencer

In reply to cgales:
Thanks cgales for informing about `uvm_field_* macros!!

In addition to it, I wanted to tell you that i missed in last post writing rand!
inside i2c_master_configuration i have declared it as
rand uvm_active_passive_enum is_active;
and after that a constraint
extern constraint is_active_agent_c;
constraint i2c_master_configuration::is_active_agent_c{ is_active==UVM_ACTIVE;}
Is it that rand you really meant?

Waiting for your reply.