In reply to Michael54:
Many people confuse overloading with overriding. You are correct that SystemVerilog does not have overloading which is defining multiple methods with the same name but different prototypes in the same or extended class. Overriding a method is what you do only by extending a class.
The uvm_object’s compare method is non-virtual and you never override it. The do_compare method is virtual and that is what you are allowed to override.