Using @* with forever block in testbench code

SystemVerilog
1 
`timescale 1ns/1ps

class c;

    bit b1;
    bit b2;

    task run();
        fork
            begin
                #1 b1 = 0;
                #1 b1 = 1;
                #1 b1 = 0;
                #1;
            end
            forever @* begin
                b2 = b1;
                $display("b1 changed");
            end
            forever begin
                @b2;
                $display("b2 changed");
            end
        join_any
        disable fork;
    endtask

endclass

module tb;

    c c1;

    initial begin

        c1 = new();
        c1.run();

        $finish;
    end

endmodule

Hi!

The code above does not compile in questasim. The error string is “** Fatal: Unexpected signal: 11.” which is not helpful. If i comment out the $display after ‘b2 = b1’, it does but the process never triggers so b2 never changes. It works as expected with aldec riviera. My question is, is this a tool issue or LRM restriction. Implicit sensitivity lists with class properties are not supported yet maybe in questa?

You can try it on edaplayground EDA Playground

2

Another tool on EDAPlayground says “Not Yet Implemented”, while another claims it ignores class properties as part of the @*, preventing the block from triggering. Only one tools seems to support it. So I would says this is a rarely requested or useful feature.

4

Thanks. @dave_59

I use it in my scoreboard class to calculate the expected output of the design. The design’s clock created internally so there is no clock that i can use.