Using Ternary operator in SVA for Temporal scenario

SystemVerilog
,
6

In reply to dave_59:

Thanks Dave .

I also observed that since if-else operates on property expression :


sequence  seq_if ;
 @( posedge clk0 ) a ##0 if( D ) B ;
endsequence

ap:assert  property( seq_if );

//  Output :  Compilation Error : "property operator inside sequence definition"

[Q] So basically if-else can only be written within a property block , right ?