Using Ternary operator in SVA for Temporal scenario

SystemVerilog
,
4

In reply to dave_59:

Hi Dave ,

One quick question :


if (boolean_expression) property_expr; 
[ OR ]
if (boolean_expression) property_expr1  else  property_expr2 ;

[Q] Why is it mentioned as property expression specifically ? Can’t it be a sequence expression ?

In the example on top :


 property  ife ;
   @( posedge clk ) a ##1 ( b || c )[->1 ]  |->  if( b )  ( ##1 d ) else ( ##1 e ) ; 
 endproperty

##1 d and ##1 e are basically sequences , so what makes it a property expression and not a sequence expression ?