In reply to ben@SystemVerilog.us:
Ben,
Unfortunately I am still not clear on the following
(1)
LRM Section 16.11 says
All subroutine calls attached to a sequence are executed at every end point of the sequence. For each end point, the attached calls are executed in the order they appear in the list.
This tells me that local_variable 'data' is assigned before calling function 'Length'
In cases where there are multiple sequence_match_items, they would execute in left to right order.
(2)
Assertion evaluation does not wait on or receive data back from any attached subroutine.
We discussed this LRM quote in [this](https://verificationacademy.com/forums/systemverilog/achieving-dynamic-delays-sva-using-subroutine). So when a time consuming task gets called as part of sequence_match_item, the assertion doesn't wait for the task to complete
(3)
The subroutines are scheduled in the Reactive region,like an action block
So doesn't this mean that void function 'Length' gets called in Reactive region ?
As void function/task don't return any value , they execute in Reactive region.
As the void function 'Length' gets called in Reactive region the assignment within it would also execute in Reactive region right ?
(4)
A side comment, module variables modified in an assertion should be used only for support logic. A user should be concerned with these timing regions
I do agree but consider a code where the sequence event control is used as triggering event to a covergroup,
And the coverpoint is sampling the value of variable assigned in subroutine.
The same scenario would exist i.e would the value prior to assignment would be sampled OR will the updated value be sampled ?