Using sequence as event contol

SystemVerilog
,
2

In reply to MICRO_91:
I modified your code slightly and added varivle f that toggles.
code: Sequence as Event control(1) - EDA Playground
wave: EPWave Waveform Viewer
SIM: T:35 Length == 0 f=0
All signals change at the clock edge in the Active region
At t35, $sampled(c)==1 and $sampled(len)==0
Thus, at t35 ##0 (1, data = len , Length( data )
Also, at t35, in the Observed region, the end point of seq is true.
Thus, always@( seq )
$display(“T:%0t Length == %0d f=%d”,$time,length, f);
Length==0 (as explained above)
$sampled(f) at the posedge clk is 1, but it changed in the Active region to 0
The $display of f is the value of f in the Observed Region, which is a 0
(this is what is sees with $display what you see NOW)
NOTE: If I change the code to
always@( seq )
$display(“T:%0t Length == %0d f=%d”,$time,length, $sampled(f));
Sequence as Event control(2) - EDA Playground
I get T:35 Length == 0 f=1


module top;
  
  bit clk , a , b , c, f ;
  
  bit [3:0] length , len ;
  
  always #5 clk = !clk;
  
  function void Length( input bit [3:0] L );
    length = L;
  endfunction
  
  sequence seq;
    bit [3:0] data;
    @(posedge clk) a ##1 b ##1 c ##0 (1, data = len , Length( data ) );  
  endsequence
  
  always@( seq )
    $display("T:%0t Length == %0d  f=%d",$time,length, f);
  
  always @(posedge clk) f<=!f;
    
  initial begin
     $dumpfile("dump.vcd"); $dumpvars;
     #5 ; a = 1 ;
    #10 ; a = 0 ; b = 1 ;
    #10 ; b = 0 ; c = 1 ; 
    #10 len = 10 ;
    #10 ;
    #2; $finish();
  end  
  
endmodule

Ben Cohen
Ben@systemverilog.us
Link to the list of papers and books that I wrote, many are now donated.

or Cohen_Links_to_papers_books - Google Docs

Getting started with verification with SystemVerilog