Using 'ref' with variables in interface

SystemVerilog
8

In reply to Babu Raghunathan:

You are going to need to show more code. this works for me

interface itf;
   logic A,B;
endinterface
module top;
   itf i();
class C;
virtual itf vitf;
   task t(ref logic arg, input string s);
      forever @arg $display(s,,arg,,$time);
   endtask // t
   task run;
      fork 
	 t(vitf.A,"A");
	 t(vitf.B,"B");
      join_none
   endtask // run
endclass // C
   C c;
   
   initial begin
      c = new();
      c.vitf = i;
      c.run();
      #1 i.A = 1;
      #1 i.A = 0;
      #1 i.A = 1;
      #1 i.B = 1;
      #1 i.B = 0;
      #1 i.B = 1;
      end
      
endmodule