I was trying to write a generic task that takes ref clk, ref data, ref en and calling this task from multiple places by passing in distint clk, data, en. In doing this, I could not send my interface (used as virtual interface) signals as input to the task and I get the error "“Invalid ref argume…

Hi Babu, You should explain your preferences and how “generic” you expect this task to be. In reality you are only asking that the names of your interface signals be generic; the functional of the signal must be the same. Can you explain with an example of what functionality you are trying to model…

In reply to dave_59 : Hi Dave, Thanks for the quick response. This is what Im doing : The generic task code just takes the data @ clk whenever en is available and dumps it to the file ‘filename’ and also sends to scoreboard. It looks like this task task_fileio (ref clk, ref data, ref en, ref f…

In reply to Babu Raghunathan : When you say “Called from outside” where is that? A class method? or top-level module? How does task_fileio send data to the scoreboard? Instead of a task, could you make fileio another interface that is bound into your interface? The ports of that interface would be …

In reply to dave_59 : When I say ‘called from outside’, I mean it is called from a class method. task_fileio sends data to scoreboard through a queue which is unloaded in scoreboard class. I do not want to use anything other than task in order to reuse the task. So, my question is, why cannot I …

In reply to Babu Raghunathan : In order to pass an argument by reference to a task, the data types of the formal and actual must match. If you have task task_fileio (ref clk, ref data, ref en, ref filename); that is understood to be the same as task task_fileio (ref logic clk, ref logic data, ref…

Agreed. But my problem is, if I declare a signal as logic abcd in an interface and try to use that as argument to task like task task_fileio(intf.abcd) I get the error message “Invalid ref argument usage as the actual argument is not a variable” So, this does not look to like a datatype mismatch…

In reply to Babu Raghunathan : You are going to need to show more code. this works for me interface itf; logic A,B; endinterface module top; itf i(); class C; virtual itf vitf; task t(ref logic arg, input string s); forever @arg $display(s,,arg,,$time); endtask // t task run; …

In reply to dave_59 : Hi Dave, I copy pasted and simulated the above code and I get the same error message “Invalid ref argument usage as the actual argument is not a variable” on both vitf.A and vitf.B. Which simulator did you use? I’m using ncsim (ver 10.2), I’m not sure if this is a simulato…

In reply to Babu Raghunathan : I guess it is a simulator issue then. You’ll need to contact Cadence. BTW, I work for Mentor, so I use Questa. Dave

In reply to dave_59 : Hi Dave, yes this is a simulator issue. I resourced to my new version of ncsim and it works. Thanks a lot for your replies, Babu

IMPORTANT NOTICE: Please be advised that the Verification Academy Forums will be offline for scheduled maintenance on Sunday, November 8th at 3:00 AM US/Pacific.

Verification Academy

Using 'ref' with variables in interface

SystemVerilog

dave_59 April 10, 2019, 9:08pm 13

In reply to krupahalani1:
You cannot pass a net(wire) by reference to a task/function.