Using non-blocking assignments for combincational logic

SystemVerilog
6

In reply to Farhad:

Maybe to avoid an infinite loop case .


bit A,C,D;
  
  always @* begin
    
    A <= D && C;  //  Previous  value  of  D  used 
    D <= !A;      //  Previous  value  of  A  used
    
    $display(" TIME : %2t D would  be  assigned  %0b " , $time , !( A ) );
    $display(" TIME : %2t A would  be  assigned  %0b \n" , $time , ( D && C ) );
    
  end
  
  initial  #40 $finish();
  
  initial  begin
    
    #5 ; B = 0 ; C = 0 ;
    
    #5 ; B = 0 ; C = 1 ; 
    
    #5 ; B = 1 ; C = 0 ;
    
    #5 ; B = 1 ; C = 1 ; 
    
  end

Since always @( * ) models combinational logic , we should use blocking assignment instead of non-blocking assignment .