Using forever for multiple execution of a task

SystemVerilog
,
1

I used forever for multiple execution of a task. I expect the simulation time to increase when I run the simulation because I used forever loop in join-none, but I see that the time stays at zero. I think the simulator stopped at if((framer_number == 4’d0) && (prev_frame_number != 4’d0) in forever loop.
How can I solve it?

always begin                                                  
    	#6.43 sys_clk = 1; 
    	#6.43 sys_clk = 0;                            
end
initial begin
		fork 
			forever begin
				if((framer_number == 4'd0) && (prev_frame_number != 4'd0))begin
					for (integer j = 0; j < NUM_NODES; j++ )begin
						micro_write(sys_clk,m_cs,m_wr,m_idata,m_addr,j+(2**(M_ADDR_W-3)), sigdata_in[j][0]);
						$display("j = %0d", j);
						$display("frame_number = %0d", framer_number);
						$display("prevframe_number = %0d", prev_frame_number);
						$fdisplay(fd_in[j],"%h",sigdata_in[j][0]);
						sigdata_in[j].pop_front();
					end
					// $display("hi");
				end
				if(debug_port_sig[NUM_NODES_LOG2 + 4])begin
					j = debug_port_sig[NUM_NODES_LOG2 + 3 : 4];
					temp_data = debug_port_sig[3:0];
					sigdata_out[j].push_back(temp_data[3:0]);
					$fdisplay(fd_out[j],"%h", temp_data);
				end
			end
		join_none
end
2

You have an infinite zero time loop. There is nothing in your code which allows time to advance.

3

no, this is part of code. there is initial block and other block. This is becuase of constraint.

4

All processes in SystemVerilog started by initial, always or fork share the same global simulation time value. If one process gets stuck in a loop with no delays, none of the other processes can proceed until loop ends and the process is ends or blocks.
You probably need some kind of blocking statement inside the forever loop waiting for data to arrive.

5

this is entire code:

`timescale 1ns / 1ps
module signaling_tb;
    parameter E1_NUM            = 16;
	logic sys_clk;

	
    class choose_time_slot;
        // rand bit[4:0] node_number[32*NUM_NODES];
		rand int time_slot_node[32*E1_NUM];
		rand int enable_node[32*E1_NUM];
		constraint enable{
			foreach(enable_node[i])
				enable_node[i] inside {[0:1]};
			foreach(enable_node[j])
				if(j % 32 == 16 || j % 32 == 31 )
					enable_node[j] == 0;
			enable_node.sum() == 16;
		
		}
		constraint time_slot{
			foreach(time_slot_node[j])
				if(enable_node[j] == 1)
					time_slot_node[j] inside {[0:15]};
			foreach(time_slot_node[i])
				foreach(time_slot_node[j])
					if( i != j)
							time_slot_node [i] != time_slot_node[j];
		}
		
		constraint prirority{
				solve enable_node before time_slot_node;
		}
		
    endclass
	initial begin
		choose_time_slot dev_timeslot;
		dev_timeslot = new();
		for(int k = 0; k < 10; k++)begin
			if(!(dev_timeslot.randomize()))
				$finish;
			$display("%d", dev_timeslot.enable_node.sum());
			foreach(dev_timeslot.enable_node[i])
				if( dev_timeslot.enable_node[i]==1)begin
					$display("index = %0d time_slot = %0d", i,dev_timeslot.time_slot_node[i]);
				end
		end
	end
	//
	
	//create sys_clk
	initial forever begin                                                  
    	#6.43 sys_clk = 1; 
    	#6.43 sys_clk = 0;                            
  	end


endmodule
6

Other than the sys_clk generation, this code is nothing like what you originally posted. That forever loop keeps the simulation running forever. In both your original and latest posts, you are generating a clock, but never using it in the code shown.

Simulation ends when there is nothing left to execute, or there is a call to $finish. You can either change that forever into repeat (1000*2) loop that say you want to run for 1000 clock cycles, or put in an initial #1000ns $finish; that says you want the simulation to run for 1000ns.