check out
http://www.asic-world.com/systemverilog/assertions24.html
Define the property, and then either use a default clocking block, or
manually point to the clocking block signals themselves; E.g:
abc_monitor_cb.vld_f
check out
http://www.asic-world.com/systemverilog/assertions24.html
Define the property, and then either use a default clocking block, or
manually point to the clocking block signals themselves; E.g:
abc_monitor_cb.vld_f