Using Class Scope Resolution operator within in-line Constraint

SystemVerilog
,
3

In reply to dave_59:

Hi Dave ,

Could you please elaborate where local:: is definitely needed over class scoped identifier

Based on your comments I could figure out code to be ::


  // Within PKG1
     class  Base ;
        ....
     endclass
 
     class Intermediate1 extends Base ;
         ...
     endclass

     class  trans  extends Intermediate1 ;
  
       rand bit [31:0]  addr ;

     endclass      
 
 // Within PKG2
     // Import PKG1
     class  Base ;
        ....
     endclass
 
     class Intermediate2 extends Base ;
         ...
     endclass

     class  seq  extends Intermediate2 ;
  
       rand bit [31:0] addr;
       trans t;
 
 function void body();
   int addr ;
 
     addr = 10 ;
        t = new();
 
   if(t.randomize() with { addr == seq::addr ; } ) // This would still work , I believe 
     $display("Success with %p",t);
   else
     $display("Fails");
 
 
 endfunction


     endclass