In reply to ben@SystemVerilog.us:
Another way of thinking is considering that assertion expressions are made from building up three layers of abstractions: booleans, sequences, and properties. When parsing the syntax of an expression, it starts at the top level looking a property, then sequence and finally a boolean expression. Note that a boolean expression by itself can be used as a single cycle sequence, and a sequence by itself can be used as a property, but the reverse is not always possible.
The and and or operators can be used for both property and sequence expressions. If one or both operands of these operators are properties, then it is considered a property operator. However, the body of a named sequence cannot contain any properties. As a result, the compiler immediately considers these as operations on sequences.
The and and or operators can be used for both property and sequence expressions. If one or both operands of these operators are properties, then it is considered a property operator. However, the body of a named sequence cannot contain any properties. As a result, the compiler considers these as operations on sequences and will not allow operands with leading clocked edges as operands to the and and or sequence operators.