Using and / or operator within Multi -clocked Sequence

SystemVerilog
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7

In reply to ben@SystemVerilog.us:

Thanks Ben .

Have a question regarding the consequent as mclocks.
When mclocks is declared as a property it works whereas there is a compilation error on declaring mclocks as a sequence : edalink

This an interesting difference between sequence and a property , however I am not clear on the reason behind it .

Would like to hear your views on it .

Thanks in advance .