Using a struct as a static config for a parameterized class

SystemVerilog
,
3

Thanks so far, this is exactly what was needed! I Extended your Version a bit to be more General, i.e. the base class has a different Parameter struct:

 
// Code your testbench here
// or browse Examples

typedef struct {
  int unsigned addr_width;
  int unsigned data_width;
} config_t;

typedef struct {
  int unsigned data_width;
} config_base_t;


class some_base #(config_base_t cfg);
  bit [cfg.data_width-1:0] some_field;
endclass


class some_class #(config_t cfg) extends some_base #('{cfg.data_width});
  bit [cfg.data_width-1:0] some_other_field;
endclass


module top;
  parameter config_t cfg = '{ 32, 64 };
  parameter config_t other_cfg = '{ 16, 32 };
  
  some_class #(cfg) obj1 = new();
  some_class #(other_cfg) obj2 = new();
  
  initial begin
    $display("obj1.some_field = %x", obj1.some_field);
    $display("obj1.some_other_field = %x", obj1.some_other_field);
    
    $display("obj2.some_field = %x", obj2.some_field);
    $display("obj2.some_other_field = %x", obj2.some_other_field);
  end
endmodule

I tried this on EDAplayground with VCS and it worked fine. Riviera gave an internal error. BTW: Do you know what happened to Questasim on EDAplayground?

One more Thing: as an Extension to this pattern is it possible to include type definitions as well somehow, so that I can use such definitions for type Parameters?

Kind of:


typedef struct#(type T = int) {
  int unsigned addr_width;
  int unsigned data_width;
} config_t;
...
class some_base #(type T = int);
  T some_field;
endclass
...
class some_class #(config_t cfg) extends some_base #(cfg::T);
  bit [cfg.data_width-1:0] some_other_field;
endclass

parameter config_t#(real) cfg = '{ 32, 64 };
...
some_class #(cfg) obj1 = new();

I know that this does not work like that, but it is supposed to give you an idea of what I mean.