Found something interesting. I need to force the clock signal in dut.
What I did is using a static variable and created a clock. Then force DUT.clock at the right time.
fork
forever begin
#(clk_p/2) ref_clk = ~ref_clk;
end
join_none
#100ns;
Problem is that if I use
force DUT.clk = ref_clk;
then dut.clk will be toggling and frequency matches ref_clk
If I use
uvm_hdl_force(string_path_dut_clk,ref_clk);
then dut clk will be constant and not toggling.
Any idea why this is happening? How could I achieve force clock using uvm_hdl_force?
Thanks!