Use the output of a module inside a class (including task (generator)

UVM
,
8

In reply to chr_sue:

the full code is:

import uvm_pkg::;
import math_pkg::;
`include “uvm_macros.svh”
//----------------
// environment env
//----------------

class env extends uvm_env;

virtual SDM_if m_if;
virtual sine_if si_if;

function new(string name, uvm_component parent = null);
super.new(name, parent);
endfunction

function void connect_phase(uvm_phase phase);
`uvm_info(“LABEL”, “Started connect phase.”, UVM_HIGH);
// Get the interface from the resource database.
assert(uvm_resource_db#(virtual SDM_if)::read_by_name(
get_full_name(), “SDM_if”, m_if));

assert(uvm_resource_db#(virtual sine_if)::read_by_name(
get_full_name(), “sine_if”, si_if));
`uvm_info(“LABEL”, “Finished connect phase.”, UVM_HIGH);

endfunction: connect_phase

task run_phase(uvm_phase phase);
phase.raise_objection(this);
`uvm_info(“LABEL”, “Started run phase.”, UVM_HIGH);

begin

  int reset_n = 0'h0;
  @(m_if.cb);
  m_if.cb.Ain <= si_if.cb.sine_out;
  m_if.cb.reset_n <= reset_n;
  repeat(2) @(m_if.cb);
  
end
`uvm_info("LABEL", "Finished run phase.", UVM_HIGH);
phase.drop_objection(this);

endtask: run_phase

endclass

//-----------
// module top
//-----------
module top;

bit clk_1mhz;
env environment;

sdm_rnm dut(.clk_1mhz (clk_1mhz));

initial begin
environment = new(“env”);
//Put the interface into the resource database.
uvm_resource_db#(virtual sdm_if)::set(“env”,
“SDM_if_if”, dut.SDM_if_if0);

clk_1mhz = 0;
run_test();

end

initial begin
forever begin
#(50) clk_1mhz = ~clk_1mhz;
end
end

initial begin
// Dump waves
$dumpvars(0, top);
end

endmodule
// SDM2 module
module sdm_rnm (Ain, clk_1mhz, reset_n, Dout);
input Ain, clk_1mhz, reset_n;
output Dout;
real Ain, dlay[2:1];
reg Dout;
real sdm_sign_val;
real sdm_sum1, sdm_sum2;
always @(negedge clk_1mhz)
begin
set_dlay (1, sdm_sum1);
set_dlay (2, sdm_sum2);
sdm_sum1 = (Ain/8.0) + dlay[1] - (sdm_sign_val/8);
sdm_sum2 = (sdm_sum1/2.0) + dlay[2] - (sdm_sign_val/8);
if (dlay[2] > 0.0) begin
sdm_sign_val = 1.0 ;
end
else if (dlay[2] < 0.0) begin
sdm_sign_val = -1 ;
end
else begin
sdm_sign_val = 0.0 ;
end
if (sdm_sign_val < 0.0) begin
Dout = 0;
end
else begin
Dout = 1;
end
end
endmodule

//---------------------------------------
// Interface for the adder/subtractor DUT
//---------------------------------------
interface SDM_if(input bit clk_1mhz, input bit reset_n, input Ain, output Dout);

clocking cb @(posedge clk_1mhz);
output Ain;
input Dout;
endclocking // cb

endinterface: SDM_if

//---------------
// Interface bind
//---------------
bind sdm_rnm SDM_if SDM_if_if0(
.clk_1mhz(clk_1mhz),
.Ain(Ain),
.Dout(Dout),
.reset_n(reset_n)
);

module sv_ams_sin_voltage_gen(output real sine_out);
parameter sampling_time = 5;
const real pi = 3.1416;
real time_us, time_s ;
bit sampling_clock;
real freq = 20;
real offset = 2.5;
real ampl = 2.5;
always sampling_clock = #(sampling_time) ~sampling_clock;
always @(sampling_clock) begin
time_us = $time/1000;
time_s = time_us/1000000;
end
assign sine_out = offset + (ampl * sin(2pifreq*time_s));
endmodule

interface sine_if(output real sine_out, input bit clk_1mhz);

clocking cb @(posedge clk_1mhz);

input sine_out;

endclocking
endinterface: sine_if

any help will be appreciated,

many thanks