Use the output of a module inside a class (including task (generator)

In reply to saketa:

Do you have a work library in the directory where you are calling vlog?
I do not use mingw compiler, I use the cygwin gcc
gcc version 5.3.0 (GCC)
see my compile log below:
vlog sine.sv sin.c -dpiheader sin.h
QuestaSim-64 vlog 10.4c Compiler 2015.07 Jul 20 2015
Start time: 18:42:54 on Apr 28,2016
vlog sine.sv sin.c -dpiheader sin.h
** Note: (vlog-2286) Using implicit +incdir+D:/SW/questa/10.4c/uvm-1.1d/…/verilog_src/uvm-1.1d/src from import uvm_pkg
– Compiling interface SDM_if
– Compiling interface sine_if
– Compiling package sine_sv_unit
– Importing package mtiUvm.uvm_pkg (uvm-1.1d Built-in)
– Compiling module top
– Compiling module sdm_rnm
– Compiling interface SDM_if
– Compiling module sv_ams_sin_voltage_gen
– Compiling interface sine_if

Top level modules:
top
– Compiling DPI/PLI C file sin.c
End time: 18:42:55 on Apr 28,2016, Elapsed time: 0:00:01
Errors: 0, Warnings: 1
** Warning: (vlog-7035) Skip generating the empty DPI header ‘sin.h’.