Use the output of a module inside a class (including task (generator)

UVM
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4

In reply to chr_sue:

hi RAGHU_BHAT,

Thank you for you suggestion
i was thinking of using interface for my sine wave module,

the updated code is:

class env extends uvm_env;

virtual SDM_if m_if;
virtual sine_if si_if;

function new(string name, uvm_component parent = null);
super.new(name, parent);
endfunction

function void connect_phase(uvm_phase phase);
`uvm_info(“LABEL”, “Started connect phase.”, UVM_HIGH);
// Get the interface from the resource database.
assert(uvm_resource_db#(virtual SDM_if)::read_by_name(
get_full_name(), “SDM_if”, m_if));
`uvm_info(“LABEL”, “Finished connect phase.”, UVM_HIGH);
assert(uvm_resource_db#(virtual sine_if)::read_by_name(
get_full_name(), “sine_if”, si_if));
`uvm_info(“LABEL”, “Finished connect phase.”, UVM_HIGH);
endfunction: connect_phase

task run_phase(uvm_phase phase);
phase.raise_objection(this);
`uvm_info(“LABEL”, “Started run phase.”, UVM_HIGH);

begin

  int reset_n = 0'h0;
  @(m_if.cb);
  m_if.cb.Ain <= si_if.cb.sine_out;
  m_if.cb.reset_n <= reset_n;
  repeat(2) @(m_if.cb);
  
end
`uvm_info("LABEL", "Finished run phase.", UVM_HIGH);
phase.drop_objection(this);

endtask: run_phase

endclass

it compile fine but when simulating the following error appear:

Virtual interface resolution cannot find a matching instance for ‘virtual SDM_if’

why thi appear?

many thanks,