Use the output of a module inside a class (including task (generator)

UVM
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39

In reply to saketa:

OK, I vahe a solution for compiling under Windows/cygwin. If you are putting a wrapper around the C-lib function it works. The C-wrapper code is here:

  1. dpi_sin.c:
    # include “math.h”
    double dpi_sin(double val) {
    return sin(val);
    }

Your SV should look like this. Consider import “DPI-C” …
2. sine.sv:

module sv_ams_sin_voltage_gen(output real sine_out);
import “DPI-C” dpi_sin = function real sin(input real x);

parameter sampling_time = 5;
const real pi = 3.1416;
real time_us, time_s ;
bit sampling_clock;
real freq = 20;
real offset = 2.5;
real ampl = 2.5;
real sin_int;
int count = 0;

always sampling_clock = #(sampling_time) ~sampling_clock;

always @(sampling_clock) begin
time_us = $time/1000;
time_s = time_us/1000000;
end

assign sine_out = sin_int;

always @(posedge sampling_clock) begin
while (count < 5) begin
freq = freq/2;
sin_int = offset + (ampl * sin(2pifreq));
$display(“freq = %0f, sine_out = %0f”, freq, sin_int);
count++;
end
$stop;
end

endmodule

  1. compile from the cygwin command line
    vlog sine1.sv sin.c -dpiheader sin.h

4 Start the Questa from the cygwin command line:
vsim -c sv_ams_sin_voltage_gen

Note Questa in Gui mode might not run, thus use "vsim -c … "