Use the output of a module inside a class (including task (generator)

UVM
,
16

In reply to saketa:

Many thanks Chr_sue
i solvet it but,

i dont know why another issuue has arising:
Failed to find ‘set_dlay’ in hierarchical name '/set_dlay

the modifyed code is:

module sdm_rnm (SDM_if SDM_if2);
  real dlay[2:1];
  reg Dout;
  real sdm_sign_val;
  real sdm_sum1, sdm_sum2;
  always @(negedge SDM_if2.clk_1mhz)
  begin
  set_dlay (1, sdm_sum1);
  set_dlay (2, sdm_sum2);
  sdm_sum1 = (SDM_if2.Ain/8.0) + dlay[1] - (sdm_sign_val/8);
  sdm_sum2 = (sdm_sum1/2.0) + dlay[2] - (sdm_sign_val/8);
  if (dlay[2] > 0.0) begin  
    sdm_sign_val = 1.0 ;
  end
else if  (dlay[2] < 0.0) begin
  sdm_sign_val = -1 ;
end
else begin 
  sdm_sign_val = 0.0 ;
end
if (sdm_sign_val < 0.0) begin
  SDM_if2.Dout = 0;
end
else begin
  SDM_if2.Dout = 1;
end
end
endmodule

the mofule rnm compile fine

Best Regards,