Use the output of a module inside a class (including task (generator)

UVM
,
10

In reply to chr_sue:

i’m using Modelsim 10.1c

i had tested the same architectur on a simple module (SUB ADD) and it work fine.

now i had done the naming change (just replacing SDM_if_if by SDM_if) but there is an issu:

Virtual interface resolution cannot find a matching instance for ‘virtual sine_if’.