In reply to srbeeram:
Most tools recognize *.v as Verilog and *.sv as SystemVerilog by default. The file extension of any file that is
`included is irrelevant as you cannot change languages at that point in the compilation. The normal convention is to use a .vh/.svh/.h extension to denote a file that is to be included and not appear on the tool command line.
I have seen some people use *.svi for an included file, but also to represent a file containing an interface. I would rather people stick with just *.sv and *.svh and use *_if.sv for an interface file. The key is to be constant within a project.
One more point if you do start using different file extensions for modules, interfaces, and packages, is that you change the tool defaults for recognizing SystemVerilog files and not use a global switch to make everything interpreted as a SystemVerilog file. Using a global switch makes it difficult to incorporate legacy Verilog code in your project, and it also allows files that were supposed to be only `included on to the command line. (That becomes important as you begin to deal with compilation units)